Complementary npn and pnp lateral transistors separated from substrate

Abstract

The invention is a pair of complementary transistors or arrays thereof and method for producing same in sub-micron dimensions on a silicon substrate selectively doped P and N type by forming intersecting slots in spaced apart relation across the P substrate regions to define semi-arrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the NPN transistor regions from the substrate. Orthogonal slots devide the semi-arrays into individual transistor active regions which are doped N and introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. The same construction obtains in the N substrate regions to form the arrays of PNP transistors. Metallization patterns complete electrical interconnections to the emitter, base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation.