The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 1992
Filed:
Dec. 03, 1990
Kazuyoshi Shinada, Yokohama, JP;
Masayuki Yoshida, Kawasaki, JP;
Takahide Mizutani, Yokohama, JP;
Naoki Hanada, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.