Memory controller as for a video signal processor

Abstract

A video signal processing system includes a memory for holding digital data, input and output channel circuitry for reading data from and writing data to the memory and processing circuits for processing data read from the memory to produce data to be written to the memory. Each of the input and output channels produces two types of memory request signals, a normal request signal and an urgent request signal. The normal request signal is produced to gain access to the data in the memory for normal read and wire operations. The urgent request signal is produced to access the memory when the processing circuitry is in a paused state waiting either to obtain data from the input channel or to provide data to the output channel. The normal read and write request signals are handled with substantially equal priority by first scheduling circuitry. The urgent request signals are handled by second scheduling circuits according to a fixed priority scheme. The use of the second scheduling circuitry disables the first scheduling circuitry.