The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 1992

Filed:

Aug. 15, 1989
Applicant:
Inventors:

Fumikazu Itoh, Fujisawa, JP;

Akira Shimase, Yokohama, JP;

Satoshi Haraichi, Yokohama, JP;

Takahiko Takahashi, Iruma, JP;

Mikio Hongo, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437173 ; 437225 ; 148D / ; 156643 ; 2504922 ; 2504923 ; 2191212 ; 21912126 ;
Abstract

A method of etching a semiconductor device having multi-layered wiring by an ion beam is disclosed which method comprises the steps of: extracting a high-intensity ion beam from a high-density ion source; focusing the extracted ion beam; causing the focused ion beam to perform a scanning operation by a voltage applied to a deflection electrode; forming a first hole in the semiconductor device by the focused ion beam to a depth capable of reaching an insulating film formed between upper and lower wiring conductors so that the first hole has a curved bottom corresponding to the undulation of the upper wiring conductor, and the upper wiring conductor is absent at the bottom of the first hole; and scanning a portion of the bottom of the first hole with the focused ion beam to form a second hole in the insulating film to a depth capable of reaching the lower wiring conductor, thereby preventing the shorting between the upper and lower wiring conductors. Further, a method of forming a hole of a predetermined shape at a surface area having a step-like portion of a semiconductor device by an ion beam is disclosed which method comprises a pre-etching step of scanning the high-level region of the step-like portion with the ion beam so that the high-level region becomes equal in level to the low-level region of the step-like portion, and a main step of scanning the whole of the surface area with the ion beam till the hole of the predetermined shape is formed in the semiconductor device.


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