Gate array architecture with basic cell interleaved gate electrodes

Abstract

A interleaved channeless gate array architecture for fabricating very large scale integration circuits created in a gate array comprises a plurality of rows or columns of basic cells wherein each of the cells includes a pair arrangement of complementary channel MOS transistors formed in adjacently disposed different conductivity type diffusion regions. A gate electrode structure for the basic cells comprises a pair of comb-shaped gate electrodes each having a plurality of parallel spatially disposed legs. Gate electrode pairs are formed over each of the basic cells in opposite opposed relation with their legs alternately interleaved relative to each other. At least one pair of alternate interleaved legs is formed across each of the basic cell diffusion regions, and metal interconnects are formed across the basic cells in a direction perpendicular relative to direction of the formed interleaved legs, and are contacted to drain/source areas of complementary channel MOS transistors and also to the gate electrode legs in gate array basic cells, as required, to form a designated circuit design.