The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 1992
Filed:
Jun. 29, 1990
Applicant:
Inventors:
Shailesh R Kadakia, Sugarland, TX (US);
Kiyoshi Mori, Stafford, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 234 ; 357 235 ; 357 236 ;
Abstract
A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with low current (longer channel length and narrower channel width), while the vertical transistor can be optimized for reading with high current (shorter channel length and wider channel width). The vertical transistor is formed in a trench (22) with a source region (15) and a sub-source VT drain region (23). The planar transistor includes the source region (15) and a co-planar PT drain region (27).