The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 1991
Filed:
Dec. 16, 1988
Eliot K Broadbent, San Jose, CA (US);
North American Philips Corp., Signetics Division, Sunnyvale, CA (US);
Abstract
A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.