The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 1991
Filed:
Feb. 08, 1991
Wojciech Maly, Pittsburgh, PA (US);
Pranab K Nag, Pittsburgh, PA (US);
Carnegie Mellon University, Pittsburgh, PA (US);
Abstract
A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile