Coplanar flash eprom cell and method of making same

Abstract

A flash EPROM cell is fabricated using a standard two polysilicon enhancement mode n-channel transistor process. An active transistor region is formed in a silicon substrate by growing a field oxide around the region. A first polysilicon layer is deposited, etched, and oxidized to form an insulated control gate electrode. A second polysilicon layer is deposited over the active transistor region and the control gate electrode and then anisotropically etched to remove all of the second polysilicon material except for a filament adjacent to the control gate electrode. The filament can be on one side of the control gate electrode or on opposing sides of the control gate electrode. Source and drain regions are formed in the active transistor region with the control gate electrode and the floating gate electrode positioned over the channel region interconnecting the source and drain regions. Two dopants (arsenic and phosphorus) are introduced into the source and drain regions with subsequent heat processing diffusing the phosphorous under a portion of the floating gate electrode. The arsenic and phosphorus form n+ and n.sup.- regions, respectively, in the source and drain regions thereby permitting higher gate-assisted avalanche breakdown in erasing the floating gate electrode. The cell is programmed by hot electron channel current injection by proper voltage biasing of the control gate and drain. The resulting cell structure can be either symmetrical or asymmetrical depending on the configuration of the floating gate filament.