Accurate delay generator having a compensation feature for power supply

Abstract

An accurate delay generator circuit for delaying the rising and falling edge of an input signal includes: a current switch having an input for receiving the input signal, first and second current inputs, and a current output; a p-channel transistor coupled to the first current input of the current switch; a first threshold voltage generator coupled to the gate of the p-channel transistor for generating a voltage equal to twice a p-channel threshold voltage with respect to VDD; an n-channel transistor coupled to the second current input of the current switch; a second threshold voltage generator coupled to the gate of the n-channel transistor for generating a voltage equal to twice an n-channel thresold voltage with respect to ground; a capacitor coupled to the output of the current switch; and an output inverter stage coupled to the output of the current switch for providing the delayed input signal. The threshold voltage generators provide constant voltages that are independent of VDD and ground from the gate to source of the p-channel and n-channel transistors respectively. The constant gate to source voltages produce relatively constant charge and discharge currents to the capacitor that in turn produce a relatively constant delay for both the rising and falling edge of the input signal. In addition, the configuration of the present invention compensates for errors in the value of the delay produced by variations in semiconductor processing parameters.