The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 1991

Filed:

Oct. 14, 1988
Applicant:
Inventors:

Mark S Myers, Portland, OR (US);

Eileen Riggs, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364200 ; 3642443 ; 3642462 ; 3642386 ; 3642408 ;
Abstract

Apparatus for queuing requests and replies on a pipelined packet bus. A RAM (212) buffers bus requests by storing packet information corresponding to each request to be sent over said bus in bus time slots allotted to each request. Three send slots (208) keep track of the state of three send requests that are stored in the RAM (212). Three receive slots (210) keep track of the state of three receive requests that are stored in the RAM (212). Nine send queue counters (230) are stepped through a series of states to track an outgoing request and to track a corresponding incoming reply. Six receive queue counters (232) are stepped through a series of states to track an incoming request and to track a corresponding reply. An output MUX (214) connected to the send and receive queues generates status information as to the state of the slots. The status information as to the state of the send and receive slots is used to control the incrementing or decrementing of the send queue counters (230) and the receive queue counters (232 ) in accordance with a predetermined system bus protocol.


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