The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1991
Filed:
May. 08, 1990
Applicant:
Inventor:
David A Baglee, Albequerque, NM (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 236 ; 357 41 ; 357 51 ;
Abstract
A dynamic read/write memory cell array employs stacked capacitors consisting of three levels of conductor separated by dielectric material. In one embodiment, the central level is a common plane, and the upper and lower levels are connected to the source regions of the pair of access transistors of two adjacent cells. In this manner, capacitors for adjacent cells occupy the same area, almost doubling the capacitor value per unit area.
Baglee, David. (1991). Stacked capacitors for vlsi semiconductor devices (U.S. Patent No. 5049958). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5049958
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile