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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5047358 B1

PDFFull Text
Date of Patent:
Sep. 10, 1991

Filed:

Mar. 17, 1989

Process for forming high and low voltage cmos transistors on a single

Applicant:
Inventors:

Walter K Kosiak, Kokomo, IN (US);

Douglas R Schnabel, Kokomo, IN (US);

Jonathan D Mann, Kokomo, IN (US);

Jack D Parrish, Kokomo, IN (US);

Paul R Rowlands, III, Kokomo, IN (US);

Assignee:

Delco Electronics Corporation, Kokomo, IN (US);

Attorney:

Wallace; Robert

Primary Examiner:

Olik Chaudhuri

Assistant Examiner:

Long Pham

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 34 ; 437 44 ; 437 57 ; 357 42 ;
Abstract

A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.

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Kosiak, Walter. (1991). Process for forming high and low voltage cmos transistors on a single (U.S. Patent No. 5047358). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5047358

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