The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 1991
Filed:
Sep. 25, 1989
Wing K Huie, North Wales, PA (US);
Alexander H Owens, Pennington, NJ (US);
David S Pan, Fremont, CA (US);
Allegro Microsystems, Inc., Worcester, MA (US);
Abstract
A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping. This results in close self-alignment of the N+ plugs and their associated DMOS and NPN transistors leading to low on-resistance, to higher IC component density, to a high throughput rate at manufacturing and low cost.