The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 1991

Filed:

Dec. 11, 1989
Applicant:
Inventors:

Sidney Liebes, Jr, Atherton, CA (US);

John Birk, Los Altos, CA (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 74 ; 357 80 ; 361400 ; 269903 ; 29832 ; 29834 ;
Abstract

A method and structure are provided for aligning SMDs to a substrate. The body of an SMD and that portion of a substrate encircled by the electrical interconnect pads each have a mating physical structure such that the SMD may be quickly placed in the general vicinity of its proper location and the mating physical features cause a precise alignment. In one embodiment, the physical features are nonsymmetrical, thereby preventing accidental placement of the SMD in an undesired rotation. In another embodiment, the physical features vary among device types, thereby ensuring that an improper device is not placed in a particular location on the substrate. In another embodiment, a component carrier is provided which includes depressions for the placement of the SMDs. A vacuum is applied to the carrier which holds each of the SMDs in place. The carrier is then placed in a desired physical relationship with the substrate such that each of the devices held in the carrier is properly aligned with the substrate. In another embodiment, a standard substrate is used without the requirement of physical mating features. Those physical mating features are provided by the use of a grid structure which is placed with proper registration on the substrate such that the physical pattern of the grid ensures proper placement of components with respect to the pads on the substrate.


Find Patent Forward Citations

Liebes, Jr, Sidney. (1991). Mechanical simultaneous registration of multi-pin surface-mount (U.S. Patent No. 5034802). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5034802

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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