Test circuit and scan tested logic device with isolated data lines

Abstract

A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test. A third interface circuit is provided for an asynchronous input of data from the logic device to the coupling circuit except during test wherein the asynchronous input is isolated from the coupling circuit. A control circuit controls the third interface and the coupling circuit during test in response to an external test enable signal. In this way, the second interface is operable during test to store data in the storing circuit for input to the logic device, and the first interface transfers test results from the logic device to the storing circuit for extraction through the serial scan path.