Carry chain incrementer and/or decrementer circuit

Abstract

A digital electronic circuit for incrementing or decrementing a binary word one count at a time. Such a circuit has an application as an address counter wherein a block of addresses in memory are stepped through one at a time. Such an address counter is found, for example, in a direct memory access (DMA) computer system integrated circuit. The count is incremented or decremented by adding or subtracting, respectively, a one from the current binary count in order to obtain a new count. A carry chain used as part of such addition circuit is separated into at least two parts and a look-ahead chain is added to work in conjunction with the carry chain to anticipate certain changes without having to wait for the carry chain to be fully sequenced. This technique reduces the time necessary to calculate the carries in the addition or subtraction process and further allows some parallel operation of the two parts of the carry chain. In a preferred implementation, the carry chain, look-ahead chain and an adder are formed in repeatable, interconnected cells wherein each chain stage has essentially a single gate and in which each cell includes the gates of two non-adjacent stages of each of the chains. This allows the circuit to be constructed in CMOS, minimizes the number of gates, and thus gate delays, and makes it easy to lay out a circuit.