The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1991
Filed:
Dec. 28, 1989
Graham W Hills, Los Gatos, CA (US);
Robert D Huttemann, Lower Macungie Township, Lehigh County, PA (US);
Kolawole R Olasupo, Kutztown, PA (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile