Dual ldd submicron cmos process for making low and high voltage

Abstract

The disclosure relates to a CMOS flow process for formation of high and low voltage transistors simultaneously in a single semiconductor chip. The low and high voltage transistors share the same gate oxide thickness and the same polysilicon gate level. This is accomplished without any additional masking steps and through the use of a separate lightly doped drain for the high voltage N-channel devices. The sources of the high voltage N-channel devices are fabricated using the more heavily concentrated LDD implant normally used for the low voltage transistors. This minimizes the source resistance of the high voltage transistor which results in higher performance through improved saturated transconductance. From a high voltage capability point of view, the flow permits the realization of a single level polysilicon single gate oxide thickness low/high voltage CMOS process.