The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1991
Filed:
Oct. 15, 1990
Applicant:
Inventor:
Mark Poret, Phoenix, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
364200 ; 3642449 ; 3642591 ; 307465 ;
Abstract
A software programmable logic array ('SPLA') is disclosed for creating a logic array which can be dynamically programmed to provide any combination of predetermined outputs from any combination of desired inputs. The foregoing is accomplished by providing a first plane of programmable bits for producing a plurality of AND terms which are input to a second plane of programmable bits for producing a plurality of OR terms, which are then input into a third plane of programmable bits for producing a plurality of outputs, each having a desired polarity.