The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1991

Filed:

Dec. 11, 1989
Applicant:
Inventors:

Jun'ichi Kinoshita, Yokohama, JP;

Nobuo Suzuki, Tokyo, JP;

Motoyasu Morinaga, Yokohama, JP;

Yuzo Hirayama, Yokohama, JP;

Masaru Nakamura, Kawaguchi, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437129 ; 148D / ; 148D / ; 148D / ; 437 59 ; 437 39 ; 437133 ; 437905 ; 437912 ; 372 50 ;
Abstract

In a monolithic OEIC in which an FET and a light-emitting device are integrated, the light-emitting device has a first clad layer, an active layer, and a second clad layer stacked on a substrate, the FET has a channel layer and source and drain layers with a high impurity concentration stacked on the substrate, etching mask layers on the source and drain layers, and a gate electrode formed on a channel layer between source and drain electrodes and the source and drain layers, the first clad layer of the light-emitting diode and the source and drain layers with a high impurity concentration of the FET are formed of the same semiconductor layer, and an active layer of the light-emitting device and the etching mask layers of the FET are formed of the same semiconductor layer.


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