The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 1991
Filed:
Mar. 31, 1989
Ping Yang, Richardson, TX (US);
Amitava Chatterjee, Dallas, TX (US);
Shian Aur, Plano, TX (US);
Thomas L Polgreen, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.