The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 1991
Filed:
May. 31, 1990
Toshikazu Inoue, Yokohama, JP;
Takashi Eshita, Ohmorinishi, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor device comprises a first semiconductor layer made of a single crystal of a first semiconductor material having a first lattice constant, a second semiconductor layer comprising a single crystal of a second semiconductor material having a second lattice constant which is different from the first lattice constant, a third semiconductor layer made of a third semiconductor material having a third lattice constant which is different from the first lattice constant, the third semiconductor layer being grown heteroepitaxially on the first semiconductor layer, a fourth semiconductor layer made of a fourth semiconductor material having a fourth lattice constant which is different from the third lattice constant, the fourth semiconductor layer being grown heteroepitaxially on the third semiconductor layer in a manner such that the second semiconductor layer is provided thereon, for preventing a first group of dislocations created in the third semiconductor layer from reaching the second semiconductor layer after passing through the fourth semiconductor layer, the fourth semiconductor layer having a thickness chosen to be larger than a critical thickness above which thickness a second group of dislocations are created in the fourth semiconductor layer, the thickness of the fourth semiconductor layer being further optimized to an optimum thickness above which thickness and below which thickness there is caused an increase of the dislocation density in the second semiconductor layer, and an active semiconductor device provided on the second semiconductor layer.