The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 1991
Filed:
May. 11, 1990
Douglas C Galbraith, Fremont, CA (US);
Jonathan W Greene, Palo Alto, CA (US);
Actel Corporation, Sunnyvale, CA (US);
Abstract
An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer/level shifter for translating the logic signals from the outside world to CMOS compatible levels. The input buffer may be placed in a high impedance state by a control signal applied to a control input. The output of the input buffer/level shifter is connected to a first data input of a two-input multiplexer. The output of the two-input multiplexer is connected to an internal bus and to the second data input of the two-input multiplexer. The select input of the two-input multiplexer is connected to a control signal, preferably to the same control signal used to enable the input buffer/level shifter. The output section of the input/output module section of the present invention includes a two-input multiplexer having a first input connected to an internal data bus, and its output fed back to its second data input. Its select input is driven from a control signal. The output of the two-input multiplexer is also connected to the input of an HCT buffer. The output of the HCT buffer is connected to an I/O pad of the integrated circuit, which may be the same pad to which the input section is connected. The slew input of the HCT buffer is driven from a signal enabling slow or fast rise times. The enable input of the HCT buffer is driven from an enable signal which may be derived from other logic signals.