The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 1991
Filed:
Nov. 03, 1989
Bruce J Tesch, Melbourne, FL (US);
Jay D Moser, Sr, Palm Bay, FL (US);
Stephen P Tam, Indialantic, FL (US);
Harris Corporation, Melbourne, FL (US);
Abstract
A single supply, TTL-compatible, class A-B signal buffer architecture comprises a multistage emitter-follower transistor circuit that is coupled between an input terminal and an output terminal capable of sinking and sourcing current to TTL specifications. A reference emitter-follower transistor stage is coupled in parallel with one of the emitter-follower transistor stages of the multistage emitter-follower transistor circuit, and a common emitter, current control transistor stage has its emitter-collector path coupled between the output terminal and ground for controlling the operation of the multistage emitter-follower transistor circuit. A differential amplifier stage, one arm of which is used to controllably forward bias the base-emitter junction of the current control transistor, has a first input coupled to the reference emitter-follower transistor stage and a second input coupled to the one emitter-follower transistor stage of the multistage emitter-follower transistor circuit. The control arm of the differential amplifier contains a voltage-dropping load impedance, to which the base of the current control transistor is coupled. A further, voltage-referenced emitter-follower provides a prescribed minimum bias voltage across the load impedance, so as to maintain the current controlling, common emitter transistor stage to be continuously conductive, so that cross-over distortion in the output signal is minimized.