The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 1991

Filed:

May. 29, 1990
Applicant:
Inventors:

Peter Gansauge, Boeblingen, DE;

Volker Kreuter, Schoenaich, DE;

Helmut Schettler, Dettenhausen, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 67 ; 357 71 ; 357 74 ; 357 80 ;
Abstract

An integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer, further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.


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