The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 1991

Filed:

Oct. 21, 1988
Applicant:
Inventors:

Ronald J Ebersole, Beaverton, OR (US);

David Johnson, Portland, OR (US);

David Budde, Hillsboro, OR (US);

Mark S Myers, Portland, OR (US);

Gerhard Bier, Herxheim, DE;

Assignees:

Siemens Ak., Berlin, DE;

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ; 3642292 ; 3642301 ; 3642428 ; 36424292 ; 3642841 ; 3642843 ;
Abstract

A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible. A replying agent assigned to the highest priority slot 1 in the pipeline queue is allowed to defer its own slot in the pipeline queue until a later time to thereby permit a transaction in Slot 2 of the pipeline queue to be completed before the one ahead of it.


Find Patent Forward Citations

Loading…