Semiconductor planarization process for submicron devices

Abstract

A method is described for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron integrated circuit devices. The method begins with the integrated circuit intermediate product having devices, such as FETs or bipolar formed therein, but before interconnection metallurgy has been formed on the principal surface of the product. The principal surface has a patterned conductive layer at its surface. The spin-on-glass sandwich now is begun to be formed by depositing a silicon dioxide coating over the patterned conductor layer. A first layer of spin-on-glass is deposited upon the silicon dioxide coating. The layer is baked at a temperature of less than about 350 degrees C. Vacuum degassing of the coating at less than about 100 mtorr and 350 degrees C. effectively overcomes the outgassing problem by removing unwanted gases in the glass layer at this point in the process. The spin-on-glass layer process just given is repeated for subsequent layers of spin-on-glass until the desired thickness of planarized spin-on-glass dielectric layer has been formed. The layers are then cured at a temperature of less than about 500 degrees C. The second layer of silicon dioxide coating over the spin-on-glass dielectric layer completes the planarization. A vacuum degassing step is performed just before the deposition of the next conductor layer.