The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 1991
Filed:
Apr. 20, 1989
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells are arranged in a matrix form. Each of the memory cells is connected to a corresponding one of a plurality of bit lines and to a corresponding one of a plurality of word lines. The ends of the bit lines are commonly connected to a programming transistor for setting a programming mode through transistors for selecting the bit lines. The transistors are connected to column decoders and the word lines are connected to a row decoder. Furthermore, the other ends of the bit lines are connected to a common connecting line through transistors for setting a test mode and the common connecting line is connected to a node between the test mode transistors and a series circuit of a transistor and a dummy memory cell in a clamp circuit. The transistor of the clamp circuit is connected to a high voltage and the series circuit is connected to the ground. In the test mode, the programming transistor and the bit line selecting transistors are turned off and the test mode transistors and the transistor connected to the clamp circuit are turned on. Thus, a test voltage is applied to the memory cells through the common connecting line, the test mode transistors and the bit lines.