The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1991
Filed:
Feb. 26, 1990
Robert K Cook, Poughkeepsie, NY (US);
Chang-Ming Hsieh, Fishkill, NY (US);
Kiyosi Isihara, Fishkill, NY (US);
Mario M Pelella, Poughkeepsie, NY (US);
Other;
Abstract
A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a base contact generally surrounding the emitter contact on the first device region and an emitter contact generally surrounded by the base contact on the second device region; and heating the device at least once to drive impurities from the base and emitter contacts on the first and second device regions into the device regions whereby to form a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region.