The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 1991

Filed:

Sep. 11, 1989
Applicant:
Inventors:

Shigeru Yamada, Yokohama, JP;

Takuya Fujimoto, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ;
U.S. Cl.
CPC ...
36518901 ; 36518909 ; 365181 ; 365203 ;
Abstract

A semiconductor memory device in which a data line and a holding circuit for storing data thereon are connected through a transmission gate comprised of an N-type MOS transistor and a P-type MOS transistor, wherein the semiconductor memory device comprises an initial potential setting circuit for setting an initial potiential on the data line prior to readout operation of data from the holding circuit; and a control circuit operative to allow the both transistors of the transmission gate to be turned on at the time of writing data into the holding circuit, and to allow one of the transistors to be turned on at the time of reading data from the holding circuit. Where a hold potential changes when data in the holding circuit has been read out onto the data line, such a change in the hold potential increases on resistance of one of the transistors which has been turned on of the transmission gate. As a result, this change in the hold potential in held down to a small value, so it does not reach the threshold voltage of the holding circuit.


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