The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 1991

Filed:

Dec. 28, 1989
Applicant:
Inventors:

David N Nichols, Fairport, NY (US);

Constantine Anagnostopoulos, Mendon, NY (US);

Charles V Stancampiano, Rochester, NY (US);

Assignee:

Eastman Kodak Company, Rochester, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 53 ; 437 27 ; 437 28 ; 437 30 ; 437931 ;
Abstract

A virtual phase CCD is fabricated in a semiconductor substrate of n-type conductivity having a layer of silicon dioxide on a surface by first forming a channel region by the implantation of boron ions. Masking regions of polycrystalline silicon are then formed on the silicon dioxide over and spaced along the channel region. Boron ions are then implanted into the substrate between the masking regions. The size of the masking regions are then increased by the addition of portions of a first photoresist layer to decrease the spacing along the channel region between the masking regions. Arsenic ions are then implanted into the channel region between the masking regions to form virtual gate regions along the surface of the channel reigon. Boron ions are then implanted into the substrate between the masking regions. The size of the masking regions is then further increased by the addition of a second photoresist layer to further decrease the spacing between the masking regions along the channel region. Boron ions are then implanted into the substrate between the masking regions. The masking regions and the silicon dioxide layer are removed and conductive gates are formed over and insulated from the substrate surface between the virtual gate regions.


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