Digital time base with differential period delay

Abstract

A digital time base with differential period delay uses the difference in period between a master oscillator and a voltage controlled oscillator phase-locked to the master oscillator to achieve small time delay increments. The oscillators are used to drive respective delay generator trigger channels that have programmable counters and state machines. A first programmable counter is a clock counter to generate a lock signal to initiate a delay sequence, the lock signals from the respective channels being input to a phase detector to generate an error signal to keep the VCO phase-locked with the master oscillator. A second programmable counter is a delay counter that is controlled by a delay state machine to generate a delay signal. The delay signal is input to respective trigger state machines to generate the desired trigger signals, the duration of the trigger signals being a function of a third programmable counter. By programming the proper values for each counter, the amount of delay for each trigger signal may be controlled with respect to the other.