Method and apparatus for preventing the erasure and programming of a

Abstract

A circuit is disclosed for preventing the erasing and programming of a nonvolatile memory device during power up and power down transitions. A power supply generator incorporating an n-channel device and a w-channel device in a wired-or configuration is coupled to a programming voltage Vpp and to a circuit voltage Vcc, and generates a node voltage Vpwr which is the greater of Vpp-Vtn and Vcc-Vtw. Vtn is the gate threshold voltage of the n-channel device, while Vtw is the gate threshold voltage of the w-channel device. The node voltage Vpwr is coupled to a reference voltage generator which provides a reference voltage, a protecting voltage, and a biasing voltage for a Vcc comparator and a Vpp comparator. The Vcc comparator and the Vpp comparator compare Vref with the output of a Vcc divide-by-two circuit and a Vpp divide-by-five cirucit, respectively. Thus, during the power up transition of the nonvolatile memory device where over-erasing may damage the memory array, the circuit forces the nonvolatile memory device into read mode, ensuring that no damaging voltage reaches the memory array. During the power down transition of a nonvolatile memory device where over-programming may accidentally erase the content of the memory array, the circuit forces the nonvolatile memory device into read mode, ensuring that the nonvolatile memory is always in a known state, and thus one can read the memory array. As such, the use of the preferred embodiment of the present invention obviates the prior art power up and power down sequencing and also affords greater protection against accidental erasure and programming than the prior art lockout detection circuit.