High-availability computer system with a predefinable configuration of

Abstract

A computer system operative during an initialization phase to initialize modules of the system and during a subsequent non-initialization phase to transfer information between the initialized modules. A module bus (MB) has 32 signal lines beginning with a least-significant-bit signal line and ending with a most-significant-bit signal line. The bus (MB) connects the modules for data transfers after the initialization phase over bidirectional address lines and data lines connected to the module bus. A system support module (SSMI) starts the initialization phase by energizing an initialization signal line (INIT). In response, a processor (GDP) generates identification command information over the bus (MB) that continas a first data record and a second data record. The first data record is comprised of bits equal to the number of signal lines in the 32-bit module bus, with only one logical one in the first data field, the position of the logical one advancing consecutively from the least significant bit position to the most significant bit position for each successive identification command generated by the processor. The second data record is an identification code uniquely identifying the one of the modules activated by the first record to receive the second record and hence its identification code.