The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 1990

Filed:

Jul. 07, 1989
Applicant:
Inventors:

Karl-Peter Ackermann, Niederrohrdorf, CH;

Gianni Berner, Baden, CH;

Assignee:

Contraves AG, Zurich, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 80 ; 357 74 ;
Abstract

In a highly integrated circuit the semiconductor chip (8) is fastened on a substrate (17) which projects on all sides only a few millimeters beyond the semiconductor chip (8). For Full dynamic testing of the circuit before insertion, connections are provided which are arranged outside the projecting substrate edge (23) with a sufficiently large grid spacing. In a first embodiment (FIG. 2D) 'lost' test connections (5) are used which are separated after testing. In a second embodiment (FIG. 3E), contact areas in the form of bumps (21) are used for testing which are arranged on the underside of the through-holes (18) lying in the chip mounting area. In this manner it is possible to realize a circuit with greatly reduced space requirement, which at the same time can be fully tested dynamically before insertion.


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