Semiconductor memory device with compact rom memory cells

Abstract

A matrix type semiconductor memory device with a higher complexity is provided which includes a p-type (or an n-type) semiconductor substrate, a plurality of n-type (or p-type) semiconductor regions formed as strips that are arranged in parallel at predetermined spacings in the surface of the substrate, the semiconductor regions provide alternating source regions and drain regions which define gate regions between the alternating regions, a first gate insulating film formed in a plurality of strips on the surface of the substrate at predetermined spacings which intersect the plurality of semiconductor regions, a plurality of first gate electrodes formed on each of the strips of the first gate insulating film, a second gate insulating film formed in a plurality of portions on the exposed surfaces of the substrate between the strips of first gate insulating film, and a plurality of second gate electrodes formed on each of the portions of the second gate insulating film without contacting the first gate electrodes. Thereby, a matrix of MIS semiconductor cells is formed, with each of the cells being provided at the intersection of each of the gate regions with one of the first and second electrodes, and the gate regions of some of the cells are selectively doped with a p-type (or an n-type) impurity substance at a higher concentration than the substrate.