The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 1990
Filed:
Jun. 07, 1988
Kazuhiro Komori, Kodaira, JP;
Takaaki Hagiwara, Hinode, JP;
Satoshi Meguro, Hinode, JP;
Toshiaki Nishimoto, Tama, JP;
Takeshi Wada, Akishima, JP;
Kiyofumi Uchibori, Hachioji, JP;
Tadashi Muto, Tachikawa, JP;
Hitoshi Kume, Musashino, JP;
Hideaki Yamamoto, Tokorozawa, JP;
Tetsuo Adachi, Hachioji, JP;
Toshihisa Tsukada, Musashino, JP;
Toshiko Koizumi, Kokubunji, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.