Unstable data recognition circuit for dual threshold synchronous data

Abstract

A circuit allows digital data acquisition instruments to recognize when dual threshold synchronous data being monitored in unstable. Each data line being monitored for unstable periods is compared with a high threshold level and a low threshold level at an acquisition probe and the results of these two comparisons are forwarded to the circuit of the present invention. Optionally, a glitch latch may be employed to cause transient crossings of the threshold to be treated as if they lasted until the next clock. The two bits of resulting information are each clocked through a short shift register consisting of two flip-flops. A gate monitoring each of these short shift registers produces an active output when the state of the two flip-flops indicates that the signal left the high state or left the low state. A third gate monitors the last flip-flop in each short register to produce an active output when the signal is neither high nor low. The outputs of these three gates are summarized by a fourth gate to provide a local unstable signal for that single data line. The results across all of the lines being monitored are ORed into an unstable signal indicating the status of all of the lines being monitored. Individual enable signals determine which lines are to be monitored for instability at any one time. A counter/timer may be used to monitor the unstable signal for setup and hold time violations with respect to a clock signal.