The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 1990

Filed:

Jun. 17, 1988
Applicant:
Inventors:

William E Earnshaw, N. Lauderdale, FL (US);

Jay Howell, Margate, FL (US);

Paul B Ripy, N. Lauderdale, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 101 ; 371 211 ; 365200 ;
Abstract

The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.


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Earnshaw, William. (1990). Error connection device for parity protected memory systems (U.S. Patent No. 4942575). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4942575

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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