Semiconductor memory device having function of checking and correcting

Abstract

A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits. The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.