The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 1990

Filed:

Nov. 30, 1988
Applicant:
Inventors:

Yasunori Yamaguchi, Tachikawa, JP;

Jun Miyake, Musahino, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
36518903 ; 36518908 ; 36523003 ; 365195 ; 36518905 ;
Abstract

A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.


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