The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 1990
Filed:
Mar. 10, 1988
H Ravindra, Milpitas, CA (US);
Suhas S Patil, Cupertino, CA (US);
Ernest S Lin, Sunnyvale, CA (US);
Mahmud M Assar, Morgan Hill, CA (US);
Dayakar Reddy, Milpitas, CA (US);
Cirrus Logic, Inc., Milpitas, CA (US);
Abstract
Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approach those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.