The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 1990

Filed:

Apr. 03, 1989
Applicant:
Inventor:

Hidetsugu Uchida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 236 ; 357 234 ; 357 42 ; 357 54 ; 357 59 ;
Abstract

In a semiconductor memory device formed on a semiconductor substrate (11), a first FET (21) is formed on a substrate. A first polysilicon film (13) serves as a gate electrode of this first FET (21). A second polysilicon film (16) is formed over the first polysilicon film (13), being separated by an insulating film (15). A third polysilicon film (20) is formed on the top and sides of the second polysilicon film (16). The third polysilicon film (20) has an impurity-doped region (19). A lower end (20a) of the third polysilicon film (20) is in contact with the first polysilicon film (13). The first, second and third polysilicon films (13, 16, 20) form a second FET (22), with the second polysilicon film (16) forming a gate electrode, and that part of the third polysilicon film (20) which is between the impurity-doped region (19) and the contacting end (20a) and adjacent to the second polysilicon film (16 ) forming a channel.


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