The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 1990
Filed:
Feb. 22, 1988
James A Sanborn, Satellite Beach, FL (US);
Janet D Sadlon, Melbourne, FL (US);
Marc H Popek, Indian Harbour Bch., FL (US);
Ralph D DiStefano, Palm Bay, FL (US);
Harris Corporation, Melbourne, FL (US);
Abstract
A process for forming a stripline interface conductor. A stripline interface conductor receives a circuit element and provides spaced-apart connections to each of the closely spaced leads of the circuit element. A first ground plane layer and an attached dielectric layer are perforated to create a first access opening and a plurality of second access openings. The plurality of second access openings are spaced at a distance from the first access opening so that closely spaced leads of the circuit element can be attached to signal traces at the first access opening and electrical connection can be made to the leads in a spaced-apart geometry at the plurality of smaller access openings. A second dielectric layer including top and bottom metallic layers is attached to the exposed side of the first dielectric layer. Before this attachment the top metallic surface of the second dielectric is etched to form the signal traces and a third access opening is formed through all three layers. The two pieces are bonded using a liquid adhesive and the first access opening is placed in registry with the third access opening. The circuit element is electrically connected to the signal traces using the portion of the signal traces exposed through the registered holes. Spaced apart connections to the leads of the circuit element are provided through the plurality of spaced-apart second access openings.