The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 1990
Filed:
Jan. 05, 1989
Abbas El Gamal, Palo Alto, CA (US);
Khaled A El-Ayat, Cupertino, CA (US);
Jonathan W Greene, Palo Alto, CA (US);
Ta-Pen R Guo, Cupertino, CA (US);
Justin M Reyneri, Los Altos, CA (US);
Actel Corporation, Sunnyvale, CA (US);
Abstract
A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conductive to custom circuit design.