The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 1990
Filed:
May. 04, 1989
Applicant:
Inventor:
Neng-Wei Wu, Hsin-Chu, TW;
Assignee:
Industrial Technology Research Institute, Taiwan, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437192 ; 437193 ; 437194 ; 437 41 ; 437228 ;
Abstract
A process for reducing gate sheet resistance in VSLI devices employs planarization and metal refilling to produce a gate of layers of polysilicon and pure metal. The polysilicon underlayer maintains the characteristics of a polysilicon gate and the metal layer reduces the gate sheet resistance. The process includes the etching back of the planarized dielectric (6) to expose the top surface of the polysilicon gate (3), the etching of the polysilicon to form a groove, and the filling of the groove with a metal, e.g. W, by selective or blanket CVD.