The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 1990
Filed:
Jul. 29, 1988
Hiroyuki Nihira, Ayase, JP;
Nobuyuki Itoh, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method of manufacturing a bipolar transistor is disclosed. A first mask material film pattern is formed on an internal base region prospective portion on a collector region of a first conductive type, and then a first conductive film is deposited. A recess around the projection of the mask film pattern are transferred on the surface of the first conductive film. After a second mask material film pattern is buried in the recess, the first conductive film is selectively etched using the second mask material pattern as a mask, thereby exposing the first mask material film pattern. The first conductive film is continuously, selectively etched by anisotropic etching using the exposed first mask material film pattern and the second mask material film pattern as etching masks to form a first opening between the two mask material film patterns. An impurity of a second conductivity type is doped through the first opening to form an external base region. The first opening is buried with a second conductive film before or after formation of the external base region. The first mask material film pattern is removed to form a second opening. After a thermal oxide film is formed on the surface of the second conductive film, an impurity of the second conductivity type is doped through the second opening, thereby forming the internal base region. An impurity of the first conductivity type is doped in the wafer through the second opening to form an emitter region.