The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 1990

Filed:

Oct. 14, 1988
Applicant:
Inventor:

Toshitaka Fukushima, Yokohama, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
375 75 ; 357 72 ; 357 59 ; 357 68 ;
Abstract

A device equivalent to a wafer-scale integrated device is achieved by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips of necessary different types are prepared, having their aluminum-wired surfaces coated with a silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces face up. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown by a PVD method. The grown silicon layer fills gaps between the IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon which is taller than the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage. The silicon nitride film is chemically removed until the aluminum wirings are exposed. An insulating layer and aluminum patterning are formed upon the exposed IC chips and filled gaps to form multi-layer wirings for interconnecting the chips and forming input/output connections. This method allows low cost wafer-scale integration higher density wirings and good heat-removal.


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