Serial dynamic memory shift register

Abstract

A serial dynamic memory shift register is configured in the form of an array of dynamic memory cells. Each dynamic memory cell is coupled to a column data bus and is addressed by an individual row command, and the data from the dynamic memory cells are transferred serially from the cells via a temporary latch. The dynamic memory cells and the temporary latch form a subarray, and a plurality of subarrays connected in series form a one-bit slice. A plurality of one-bit slices connected in parallel to receive the multiple bits of a data word in parallel forms a one-word slice. Each one-word slice has an data input latch to transfer data from an input data bus to the one-word slice, and an data output latch to transfer data from the one-word slice to an output data bus. A plurality of one-word slices connected in parallel complete the serial dynamic memory shift register, with one-half of the one-word slices being anti-phase with the other half of the one-word slices to provide a continuous input/output flow of data. Data words are read sequentially into the one-word slices, shifted serially along each one-word slice, and then read sequentially out of the one-word slices to perform the shift process at the clock rate.